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maxshiyan
- 大学vhdl语言实验大全,基于max-plus2平台,内有8-3译码器,8位加法器,数字钟，数码显示，74ls138，8，4位计数器，d，rs触发器，加法器，交通灯等，此原码基于长江大学可编程器件实验箱,如要运行在其他平台上需要重新定义管脚-University VHDL language experiment Daquan, based on the max-plus2 platform within 8-3 decoder, 8 Adder, digital clock, digital d
S3Demo
- Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simpl
djkrs
- d,jk,rs触发器的vhdl语言实现，简单明了
rs_encoder
- 一个很不错RS编码，用于DVB的信道编码，用VHDL语言编写，在FPGA上通过验证。
uart_transmitter
- Very good info. for RS-232 transmitter VHDL code .
uart_receiver
- Very good info. for RS-232 receive VHDL code .
ECHO_DE2
- Very good info. for RS-232 echo VHDL code .
mimasuo
- vhdl 实验报告 verilog rs触发器 vhdl实验 vhdl 实验 报告 verilog rs触发器 vhdl实验
RS_255_223_ENCODER
- RS(255,223)编码器程序 从一本书上看到的，很不错的-RS(255,223) encode , very good good good
RS3123
- Reed- So lomon (RS) 码是一种重要的纠错码, 它对随机性和突发性错误有极强的纠错能力, 广泛应用于 数字视频广播(DVB) 系统和其它数字通信领域。给出了一种GF (25) 域上的RS (31, 23) 编码器的实现算法, 介绍 了用现场可编程门阵列(FPGA ) 实现RS 编码器的原理和过程, 并给出了实现电路及其仿真的输出波形。-Reed-So lomon (RS) code is an important error-correcting code, its ra
rs_dec_enc_latest.tar
- RS encoder decoder on vhdl
RSdecFlash_100722
- RS(511,495) decoder for NAND flash controller,decoding steps: (1)syndrome (2)Berlekamp-Massey (3)chien (4)forney
28538604-Spartan-3E-MATLAB-Interface-Documentatio
- Documentation VHDL communication RS-232 with the spartan 3
qiangdaqi
- 多路抢答器 VHDL语言设计 抢答器是各类竞赛常用的仪器设备之一，它能快速、准确地判决并显示出第一抢答者。本文作者采用MAXPLUSII 软件和MAX7000S芯片，提出了一种四路抢答器的设计方案。该方案具有判断准确、硬件电路简单、容易实现等优点。 关键字：抢答器 竞争 RS触发器 EDA -Multiple Responder Responder VHDL language design competition of various kinds of equipment used, i
working_code
- rs 485 working code for project
(255_223)-RS-decoder
- 使用VHDL实现（255,233）的RS硬件译码器，详细地介绍了(255，223)RS码硬件译码器的实现流程，并且分析了影响处理速率提高的瓶颈因素，采用RiBM算法实现译码-Use VHDL (255,233) RS hardware decoder, a detailed descr iption of the (255,223) RS code hardware decoder implementation process, and analyze the bottleneck factor
rs(63-45)
- 用VHDL实现的RS（63,45）编码器，已经用ISE和questasim编译仿真通过。对45个信息位进行编码。-VHDL implementation of the RS (63,45) encoder has been compiled with the ISE and questasim through simulation. Of 45 information bits are encoded.
RS-encoder
- RSC encoder in VHDL. Hope it helpful.
RS
- 802.16d的RS编解码的VHDL实现-802.16d RS encoding and decoding in VHDL
rs-code
- VHDL Code for D-Flip Flop & Matching Unit